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  1. DEC Alpha - Wikipedia › wiki › DEC_Alpha

    Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computer (CISC) as well as be a highly competitive RISC processor for Unix workstations and similar markets.

    • 1992; 29 years ago
    • RISC
  2. Digital Equipment Corporation - Wikipedia › wiki › Digital_Equipment_Corporation

    DEC initially started work on Alpha as a way to re-implement their VAX series, but also employed it in a range of high-performance workstations. Although the Alpha processor family met both of these goals, and, for most of its lifetime, was the fastest processor family on the market, extremely high asking prices [7] [ better source needed ] were outsold by lower priced workstation chips from Intel and IBM/Motorola.

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  4. DEC Alpha - Wikipedia › wiki › DEC_Alpha

    DEC Alphaは、Alpha AXPとしても知られ、ディジタル・イクイップメント・コーポレーション (DEC) の64ビット RISC 命令セットアーキテクチャ (ISA) であり、32ビット VAX CISC ISA とその実装を置換すべく設計された。

    • 64ビット
    • RISC
    • 1992年
    • DEC
  5. DEC Alpha – Wikipédia, a enciclopédia livre › wiki › DEC_Alpha

    DEC Alpha Origem: Wikipédia, a enciclopédia livre. O DEC Alpha, também conhecido como Alpha AXP, é um microprocessador de 64 bit construído na arquitetura RISC. Ele foi desenvolvido pela Digital Equipment Corporation (DEC).

    • 1992 até o presente
  6. DEC Alpha – Wikipedia › wiki › DEC_Alpha

    DEC Alpha -prosessori Alpha AXP (myös DECchip, DEC Alpha tai pelkkä Alpha) on Digital Equipment Corporationin 1990-luvulla kehittämä RISC - suoritinarkkitehtuuri, joka suunniteltiin VAX -arkkitehtuurin seuraajaksi DEC:n työasema- ja palvelinkoneisiin.

  7. DEC Alpha – Wikipédia › wiki › DEC_Alpha

    A DEC Alpha regiszterei Az architektúra 32 egész (integer) regisztert és 32 lebegőpontos regisztert definiál, a programszámláló, két zárolási segédregiszter és egy lebegőpontos vezérlőregiszter (floating-point control register, FPCR) mellett.

    • 64 bites
    • RISC
  8. DEC Alpha - WikiMili, The Best Wikipedia Reader › en › DEC_Alpha

    Alpha, originally known as Alpha AXP, is a 64-bitreduced instruction set computing(RISC) instruction set architecture(ISA) developed by Digital Equipment Corporation(DEC), designed to replace their 32-bitVAXcomplex instruction set computer(CISC) ISA. Alpha was implemented in microprocessorsoriginally developed and fabricatedby DEC.

  9. DEC Alpha | Microsoft Wiki | Fandom › wiki › DEC_Alpha
    • History
    • Design Principles
    • Registers
    • Data Types
    • Memory
    • Instruction Formats
    • Instruction Set
    • Extensions
    • Implementations
    • Performance

    Alpha was born out of an earlier RISC project named PRISM, itself the final product of several earlier projects. PRISM was canceled after a proposal by the Palo Alto design team to build the Unix-only workstations (DECstation 3100) on a MIPS R2000 processor, allowing the DECstation to come to market sooner. Among the differences between PRISM and other RISC processors, however, was that PRISM supported a user-programmable microcode known as Epicode. PRISM had been designed with the intent of releasing a new operating system along with it, known as Mica, which would allow it to run "native" programs at full speed while also supporting Digital's existing VMS programs from the VAXafter minor conversion. DEC management doubted the need to produce a new computer architecture to replace their existing VAX and DECstation lines, and eventually ended the PRISM project in 1988. By the time of cancellation, however, second-generation RISC chips (such as the newer SPARC architecture), were offe...

    The Alpha architecture was intended to be a high-performance design. Digital intended the architecture to support a one-thousandfold increase in performance over twenty-five years. To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have: 1. Branch delay slots 2. Suppressed instructions 3. Byte load or store instructions (later added with the Byte Word Extensions (BWX))

    The architecture defined a set of 32 integer registers and a set of 32 floating-point registers in addition to a program counter, two lock registers and a floating-point control register (FPCR). It also defined registers that were optional, implemented only if the implementation required them. Lastly, registers for PALcodewere defined. The integer registers were denoted as R0 to R31 and floating-point registers were denoted as F0 to F31. The R31 and F31 registers were hardwired to zero and writes to those registers by instructions are ignored. Digital considered using a combined register file, but a split register file was determined to be better as it enabled two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating point registers. A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports....

    In the Alpha architecture, a byte was defined as an 8-bit datum, a word as a 16-bit datum, a longword as a 32-bit datum, a quadword as a 64-bit datum and an octaword as a 128-bitdatum. The Alpha architecture originally defined six data types: 1. Quadword (64-bit) integer 2. Longword (32-bit) integer 3. IEEE T-floating-point (double precision, 64-bit) 4. IEEE S-floating-point (single precision, 32-bit) To maintain a level of compatibility with VAX, the 32-bit architecture the Alpha succeeded, two VAX data types were included: 1. VAX G-floating point (double precision, 64-bit) 2. VAX F-floating point (single precision, 32-bit) The Alpha had some provision for future expansion of the instruction set to include 128-bit data types.

    The Alpha has a 64-bit linear virtual addressspace with no memory segmentation. Implementations can implement a smaller virtual address space with a minimum size of 43 bits. Although the unused bits were not implemented in hardware such as TLBs, the architecture required implementations to check if they are zero to ensure software compatibility with implementations that implemented a larger or the full virtual address space.

    The Alpha ISA has a fixed instruction length of 32 bits. It has six instruction formats. The integer operate format is used by integer instructions. It contains a 6-bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand. Next is a 3-bit field which is unused and reserved. A 1-bit field contains a "0", which distinguished this format from the integer literal format. A 7-bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to. The register fields are all 5 bits long, required to address 32 unique locations, the 32 integer registers. The integer literal format is used by integer instructions which use a literal as one of the operands. The format is the same as the integer operate format except for the replacement o...

    Control instructions

    The controlinstructions consist of conditional and unconditional branches, and jumps. The conditional and unconditional branch instructions use the branch instruction format, while the jump instructions use the memory instruction format. Conditional branches test the least significant bit of a register is set or clear, or compare a register as a signed quadword to zero, and branch if the specified condition is true. These conditions available for comparing a register to zero are equality, ine...

    Integer arithmetic

    The integer arithmetic instructions perform addition, multiplication, and subtraction on longwords and quadwords; and comparison on quadwords. There is no instruction(s) for division as the architects considered the implementation of division in hardware to be adverse to simplicity. In addition to the standard add and subtract instructions, there are scaled versions. These versions shift the second operand to the left by two or three bits before adding or subtracting. The Multiply Longword an...

    Logical and shift

    The logical instructions consist of those for performing bitwise logical operations and conditional moves on the integer registers. The bitwise logical instructions perform AND, NAND, NOR, OR, XNOR, and XOR between two registers or a register and literal. The conditional move instructions test a register as a signed quadword to zero and move if the specified condition is true. The specified conditions are equality, inequality, less than or equal to, less than, greater than or equal to, and gr...

    Byte-Word Extensions

    Later, the Alpha included byte-word extensions, a set of instructions to manipulate 8-bit and 16-bit data types. These instructions were first introduced in the 21164A (EV56) microprocessor and are present all subsequent implementations. These instructions performed operations that previously required multiple instructions to implement, which improved code density and the performance of certain applications. BWX also made the emulation of x86 machine code and the writing of device driverseasier.

    Motion Video Instructions

    Motion Video Instructions (MVI) was an instruction set extension to the Alpha ISA that added instructions for single instruction, multiple data (SIMD) operations. Alpha implementations that implement MVI, in chronological order, are the Alpha 21164PC (PCA56 and PCA57), Alpha 21264 (EV6) and Alpha 21364 (EV7). Unlike other SIMD instruction sets of the same period such as MIPS' MDMX or Sun Microsystems' Visual Instruction Set, MVI was a simple instruction set composed of a few instructions that...

    Floating-point Extensions

    Floating-point extensions (FIX) was an extension the Alpha Architecture. It introduced nine instructions for floating-point square-root and for transferring data to and from the integer registers and floating-point registers. The Alpha 21264(EV6) was the first microprocessor to implement these instructions.

    At the time of its announcement, Alpha was heralded as an architecture for the next 25 years. While this was not to be, Alpha has nevertheless had a reasonably long life. The first version, the Alpha 21064 (otherwise known as the EV4) was introduced in November 1992 running at up to 192 MHz; a slight shrink of the die (the EV4S, shrunk from 0.75 µm to 0.675 µm) ran at 200 MHz a few months later. The 64-bit processor was a superpipelined and superscalar design, like other RISC designs, but nevertheless outperformed them all and DEC touted it as the world's fastest processor. Careful attention to circuit design, a hallmark of the Hudson design team, like a huge centralized clock circuitry, allowed them to run the CPU at higher speeds, even though the microarchitecture was fairly similar to other RISC chips. In comparison, the less expensive Intel Pentiumran at 66 MHz when it was launched the following spring. The Alpha 21164 or EV5 became available in 1995 at processor frequencies of...

    To get an idea of the performance of Alpha-based systems, here are some SPEC performance numbers (SPECint95, SPECfp95). Note that the SPEC results claim to report the measured performance of a whole computer system (CPU, bus, memory, compiler optimizer), not just the CPU. Also note that the benchmark and scale changed from 1992 to 1995. However, the idea here is to give a rough idea of the Alpha architecture (64-Bit) performance compared with HP (64-Bit) and Intel-based offerings (32-Bit) at the same time. Perhaps the most obvious trend is that while Intel could always get reasonably close to Alpha in integer performance, in floating point performance the difference was considerable. On the other side, HP (PA-RISC) is also reasonably close to Alpha, but these CPUs are running at significantly lower clock rates (MHz).

  10. Tru64 UNIX - Wikipedia › wiki › Tru64_UNIX

    Tru64 UNIX is a discontinued 64-bit UNIX operating system for the Alpha instruction set architecture (ISA), currently owned by Hewlett-Packard (HP). Previously, Tru64 UNIX was a product of Compaq, and before that, Digital Equipment Corporation (DEC), where it was known as Digital UNIX (originally DEC OSF/1 AXP).

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